This invention relates to power-up reset circuits for logic circuits, and more particularly, to power-up reset circuits for use with power supplies of any given ramp rate.
In certain integrated circuit (IC) design applications, it is desirable or even necessary to provide a reset signal for certain types of logic elements. These logic elements are typically memory circuits of one type or another which will remain in a certain state once having been set to that state. Such elements are flip-flops, counters, timers and other similar circuits. To ensure proper operation of the circuit which contains such elements, a reset signal is typically provided during power-up of the circuit to set these elements to a certain desired condition. Normally, it is desirable to have this reset occur automatically during power-up, that is, during the period of time when the voltage from the power supply is transitioning from zero volts to the nominal voltage used to power the circuit.
Although power-up reset circuits which automatically generate a reset signal during power-up are known, these circuits have exhibited several problems. In many cases, the power-up circuit is useful only with power supplies having a certain ramp rate. The term ramp rate is used to describe the rate at which the voltage output level of the power supply changes from zero to its nominal voltage from the time it is turned on until it reaches a steady state condition. Another problem exhibited by many existing power-up reset circuits is that they continue to draw power even after the reset signal has been generated. This is particularly undesirable for CMOS circuits which are battery powered. A further problem that many of these reset circuits have exhibited is that they require certain passive components such as resistors or capacitors in addition to standard geometry devices such as MOSFETs. Consequently, more sophisticated and expensive manufacturing processes for generating the integrated circuit must be utilized to integrate the passive components with the standard geometry devices. For CMOS Gate Array/Standard Cell implementations which are manufactured using basic CMOS processing techniques, the passive components cannot be integrated with the standard geometry devices and must be provided externally.
It is therefore an object of the invention to provide a power-up reset circuit which is functionally independent of the ramp rate of the power supply used.
It is another object of the invention to provide a power-up reset circuit which draws little or no stand-by current.
It is a further object of the invention to provide a power-up reset circuit which is easily implemented for either a CMOS Gate Array or a CMOS Standard Cell utilizing basic CMOS processing techniques.
It is an additional object of the invention to provide a power-up reset circuit which can be implemented on a relatively small die area.
Another object of the invention is to provide a power-up reset circuit whose functionality is independent of the typical range of process variations and temperature range applications.
A power-up reset circuit of this invention generates a reset signal during a power-up cycle of a power supply having a source voltage potential and a source voltage reference. A first means senses the source voltage potential and generates the reset signal at an output when the source voltage potential rises above a threshold level. The power-up reset circuit further has means for coupling an input of the first sensing means to the source voltage potential to permit a voltage at the first sensing means' input to follow the source voltage potential during an initial rise of the source voltage potential. A second sensing means senses the source voltage potential and generates a time delayed signal at an output when the source voltage potential rises above a predetermined level. A terminating means has an input coupled to the output of the second sensing means and generates a termination signal at an output coupled to the input of the first sensing means to terminate the reset signal in response to the time delayed signal. A feedback switch has an input coupled to the output of the first sensing means and couples the terminating means to one of the source voltage potential and the source voltage reference in response to the reset signal and decouples the terminating means from the one of the source voltage potential and source voltage reference in response to the termination of the reset signal.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.